The present invention relates generally to semiconductor manufacturing and, more particularly, to compensating for layout dimension effects in semiconductor device modeling.
The manufacturing of semiconductor devices may involve many process steps. For example, semiconductor fabrication typically involves processes such as deposition processes, etching processes, thermal growth processes, various heat treatment processes, ion implantation, photolithography, etc. Such processes may be performed in any of a variety of different combinations to produce semiconductor devices that are useful in a wide variety of applications.
In general, there is a constant drive within the semiconductor industry to increase the operating speed and efficiency of various integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds and efficiency. This demand for increased speed and efficiency has resulted in a continual reduction in the size of semiconductor devices, e.g., transistors, as well as the packing density of such devices on an integrated circuit device. That is, many parameters of a typical field effect transistor (FET), e.g., channel length, junction depths, gate insulation thickness, and the like, are reduced. For example, all other things being equal, the smaller the channel length of the transistor or the thinner the gate insulation layer, the faster the transistor will operate. Thus, there is a constant drive to reduce the size, or scale, of the components of a typical transistor to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors.
Modern field effect transistors comprise a gate electrode, a gate insulation layer, a source region and a drain region. When an appropriate voltage is applied to the gate electrode, a channel region is formed between the source region and the drain region and electrons (or holes) flow between the source region and drain region. The source and drain regions of such transistors are normally the same. For example, for an NMOS transistor, both the source and drain regions are formed by introducing an N-type dopant material, e.g., arsenic, into the semiconductor material. For a PMOS transistor, the source and drain regions are formed by introducing a P-type dopant material, e.g., boron, into the semiconductor material.
Typically, during the design of a semiconductor device, various circuit elements, such as transistors, are simulated to predict their characteristics, such as threshold voltage, drain-to-source resistance, breakdown voltage, etc. FIGS. 1A and 1B illustrate devices 100 and 120, respectively, that may be simulated using a model. The device 100 is a three-finger transistor having three lines 102, 104, 106 extending from a base member 108. The lines 102, 104, 106 and base member 108 define a transistor gate electrode. The lines 102, 104, 106 intersect an active region 110. In defining the devices for modeling purposes, the width, W1, of the active region and the length (i.e., commonly referred to as a channel length), L1, L1, L3, of the lines 102, 104, 106 are defined.
The device 120 includes two lines 122, 124 each having a length, L4, L5, intersecting an L-shaped active region 126 having widths, W2, W3. Based on the specified parameters, a model may be used to predict the characteristics of the devices. Of course, many other parameters of the devices 100, 120 are specified in addition to the length and width dimensions, such as material of construction, doping profiles, etc.
The use of device models provides designers with information about the expected performance characteristics of the integrated circuit prior to its implementation in an actual semiconductor device. Using this information, design parameters may be changed and refined prior to any actual fabrication.
However, in actual fabricated devices, the devices are not fabricated as shown in the ideal geometries of FIGS. 1A and 1B. For instance, the corners of the devices 100, 120, such as corners 112 where the lines 102, 104, 106 intersect the base member 110 or the corner 128 of the L-shaped active region 126 are typically not perfectly square. Modeling the devices 100, 120 using ideal length and width parameters results in some degree of inaccuracy, because it does not account for the corner rounding. This variation between the simulated ideal devices and the actual fabricated devices induces variation between the predicted performance parameters and the actual performance parameters of the fabricated devices. As device geometries continually decrease, these small modeling inaccuracies have an increasingly noticeable effect on the performance of the completed devices.
This section of this document is intended to introduce various aspects of art that may be related to various aspects of the present invention described and/or claimed below. This section provides background information to facilitate a better understanding of the various aspects of the present invention. It should be understood that the statements in this section of this document are to be read in this light, and not as admissions of prior art. The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.